A. Field of the Invention
This invention relates generally to the design and testing of digital electronic circuits, and more particularly to the design and verification of customizable logic devices, such as Application Specific Integrated Circuits (ASICs).
B. Statement of Related Art
Digital electronic circuits may be designed using a variety of methods, which include, but are not limited to, schematic capture, VISIC Hardware Description Language (VHDL), Verilog.RTM. Hardware Description Language, and hand drawn schematic diagrams. Once a logic circuit is developed, it is desirable to simulate its performance by providing circuit stimulating test vectors as inputs to the circuit model. This simulation may be done using a variety of commercially available products, such as Mentor Graphics Quicksim II.RTM., Ikos' hardware accelerator, Cadence Design Systems' Verilog XL.RTM. etc. Background references relating to the subject of design and verification of electronic circuits include U.S. Pat. Nos. 5,452,227; 5,349,539; 5,325,309; 4,590,581; and the textbook Thomas E. Dilinger, VLSI Engineering, Prentis Hall (1988), Chapter 4, pp. 91-135, which are incorporated by reference herein.
In designing digital electronic circuits, it is customary to validate and test the architecture and instruction set using a behavioral model of the circuit which implements this architecture. Later in the development process, lower level models such as a structural model and a Register Transfer (RTL) model may be designed. Behavioral models are useful in circuit design because certain statements in VHDL and Verilog are not directly synthesizeable from logic gates, and hence a complex software model, i.e., a behavioral model, must be built to model these circuits. In essence, the behavioral model is like a black box, as it generates the outputs of the circuit given a set of possible inputs.
As the design is simulated, the circuit outputs need to be examined in order to verify that they respond in the manner expected by the designer. This verification process may be performed many ways, including, but not limited to, visual inspection of ASCII data files, representing circuit outputs (tabular data files), visual inspection of graphical waveforms of circuit outputs, or any other method of determining circuit correctness. These verifications may be done either post-simulation, or interactively. In post simulation testing and verification, a complete simulation is performed, data is captured for all signals, and the data verified after simulation. In iterative testing and verification, the simulation is run for a short time, the simulation is paused in order to verify the current simulation output data, continue simulation, pause to verify new output data etc.
Systematic digital electronic circuit design and test techniques usually approach the design on a functional block by block basis. That is, one block is designed, simulated and verified, before proceeding to the next block. Also, all new blocks are designed, simulated and verified, before interconnecting with previously tested blocks. It becomes apparent that as each new block is added to the design, earlier blocks must also be re-verified to ensure they still function as desired and that they have not been effected by newly-added blocks.
The verification process can thus become very repetitive and tedious as the design increases in terms of size, function and complexity. It is thus desirable to provide an automated or semi-automated methodology for module verification.
Prior art simulation systems provide this capability through the use of additional designer-supplied signals referred to as expected outputs (EO). Each EO represents the logical value of each corresponding circuit output which is expected to result after the application of circuit input stimulus. This provides an answer-key-like pattern of what the correct response for each signal, over all simulation time, should be. When the circuit is simulated and verified, these simulators associate the EO with the respective signal and continuously compare them throughout the simulation. When a miscompare between the EO and its associated signal occurs, the simulator may respond appropriately. Appropriate responses may include, but are not limited to, incrementing a counter of all currently accumulated errors, halting simulation, pausing simulation, terminating simulation, generating an error report, etc. These responses depend on the type of verification (viz. interactive or post-processing) and the capabilities of the simulator.
This method of testing over all time is not always desirable, as it is very difficult and impractical to provide an exact representation of each signal under all conditions (i.e. different voltages, different temperatures, each affecting subtle timing shifts, causing the circuit output to differ from the EO). It is therefore desirable to partition the simulation into discrete simulation periods, each the same fixed duration long, and only verify the circuit output during a designer defined portion of this simulation period. For example, if a simulation period is defined as a 20 nS interval, the simulation period may be referred to, relative to the start of each period, as 0 nS (start)-20 nS (end). The actual verification time (also known as the "data strobe" or "strobe window") may take place only during, say, time 15 ns-19 ns. A strobe window, possibly different for each signal, would be able to be specified by the designer for every signal. This allows the designer to control when each signal is tested.
Additionally, a designer may not be interested in the output of a signal from one function, say function B, while the designer is verifying another function, say function A. In this manner the designer desires the ability to suppress a miscompare on demand or prevent an error condition from being detected. This technique is referred to herein as "masking" a signal output.
The object of this invention is to provide a system which performs automatic iterative digital circuit verification.
Another object of this invention is to provide a system which performs automatic circuit verification over all logic levels 1 (logic high), 0 (logic low), HI-Z (High impedance).
Another object of this invention to provide a testing and verification system permits designer-specified test parameters to increase the ease and efficiency of the testing and verification process. The present invention enables the designer to specify test periods, to specify verification strobe windows within a test period, and the capability to mask or prevent miscompares of individual signals at the designers discretion.
Another object of the invention is to decrease the time required to verify a circuit using these simulators, and while increasing the repeatability and completeness of each verification operation. This invention also enables less-sophisticated and less expensive simulators to use the teachings of the present invention to enjoy advanced features found only in more complex and costly simulators.
These and other objects, advantages and features of the present invention will be more apparent from the following detailed description of the preferred embodiment of the invention.